On chip weighted random patterns

Author

Savir, Jacob

Author_Institution

Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA

fYear

1997

fDate

17-19 Nov 1997

Firstpage

344

Lastpage

352

Abstract

This paper describes the design details, operation, cost, and performance of a distributed weighted pattern test approach at the chip level. The traditional LSSD SRLs are being replaced by WRP SRLs designed specifically to facilitate a weighted random pattern (WRP) test. A two-bit code is transmitted to each WRP SRL to determine its specific weight. The WRP test is then divided into groups, where each group is activated with a different set of weights. The weights are dynamically adjusted during the course of the test to “go after” the remaining untested faults. The cost and performance of this design system are explored on three pilot chips. Results of this experiment are provided in the paper

Keywords

automatic testing; built-in self test; integrated circuit testing; logic design; logic testing; random processes; ATPG; BIST; chip weighted random patterns; cost; distributed weighted pattern test; performance; pilot chips; two-bit code; Built-in self-test; Circuit faults; Circuit testing; Costs; Decoding; Electrical fault detection; Face detection; Fault detection; Jacobian matrices; Logic design;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1997. (ATS '97) Proceedings., Sixth Asian

Conference_Location

Akita

ISSN

1081-7735

Print_ISBN

0-8186-8209-4

Type

conf

DOI

10.1109/ATS.1997.643981

Filename

643981