DocumentCode :
3221347
Title :
Simulation and Optimization of Power DMOS Transistors Parameters
Author :
Emelyanov, Victor A. ; Baranov, Valentine V. ; Rubtsevich, Ivan I. ; Anufriev, Dmitry L.
Author_Institution :
Res. & Production Corp. "Integral",, Minsk
Volume :
1
fYear :
2006
fDate :
5-7 Sept. 2006
Firstpage :
666
Lastpage :
670
Abstract :
At present power DMOS transistors are regarded as one of the most prospective components for many power-saving devices. When developing power DMOS transistors, which parameters are analogs of IRL640, "transistor factory" of RPC "integral" used the skills of physical and layout simulation and design of low-power LSI having N-channel MOS transistor structures. Based on this approach and using the developed original software, conducted was optimization of parameters of solid-state structure of power DMOS transistors of KP728E1 type. In particular, minimized were the resistance values between the drain and source areas in the transistor "open" state, output and pass-by capacitances of cell transistor structure when maintaining other parameters at the set level. Given are resistive and capacitance models of a DMOS transistor. Resistance of a conductive channel in an elementary cell of a DMOS transistor was calculated as the sum of capacitances of a solid-state structure, including herein the induced channel of a horizontal N-MOS transistor, and the cell\´s capacitances are optimized taking into account SiO2 thickness in different parts of the structure
Keywords :
MOS integrated circuits; MOSFET; large scale integration; low-power electronics; power transistors; silicon compounds; IRL640; KP728E1; LSI; N-MOS transistor; N-channel MOS transistor; RPC; SiO2; cell transistor structure; conductive channel; elementary cell; layout simulation; pass-by capacitances; physical simulation; power DMOS transistors; power-saving devices; solid-state structure; transistor factory; Algorithm design and analysis; Boron; Breakdown voltage; Capacitance; Impurities; MOSFETs; Oxidation; Production facilities; Solid state circuits; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Systemintegration Technology Conference, 2006. 1st
Conference_Location :
Dresden
Print_ISBN :
1-4244-0552-1
Electronic_ISBN :
1-4244-0553-x
Type :
conf
DOI :
10.1109/ESTC.2006.280076
Filename :
4060800
Link To Document :
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