Simulation and Optimization of Power DMOS Transistors Parameters

At present power DMOS transistors are regarded as one of the most prospective components for many power-saving devices. When developing power DMOS transistors, which parameters are analogs of IRL640, "transistor factory" of RPC "integral" used the skills of physical and layout simulation and design of low-power LSI having N-channel MOS transistor structures. Based on this approach and using the developed original software, conducted was optimization of parameters of solid-state structure of power DMOS transistors of KP728E1 type. In particular, minimized were the resistance values between the drain and source areas in the transistor "open" state, output and pass-by capacitances of cell transistor structure when maintaining other parameters at the set level. Given are resistive and capacitance models of a DMOS transistor. Resistance of a conductive channel in an elementary cell of a DMOS transistor was calculated as the sum of capacitances of a solid-state structure, including herein the induced channel of a horizontal N-MOS transistor, and the cell\´s capacitances are optimized taking into account SiO₂ thickness in different parts of the structure