Author :
Min, Yinghua ; Zhao, Zhuxing ; Li, Zhongcheng
Author_Institution :
CAD Lab., Acad. Sinica, Beijing, China
Abstract :
The industry has accepted IDDQ testing to detect CMOS IC defects. While IDDT testing needs more research to be applicable in practice. However, it is noticed that observing the average transient current can lead to improvements in real defect coverage. This paper presents a formal procedure to identify IDDT testable faults, and to generate input vector pairs to detect the faults based on Boolean process. It is interesting to note that those faults may not be detected by IDDQ or other test methods, which shows the significance of IDDT testing
Keywords :
Boolean algebra; CMOS logic circuits; electric current measurement; fault location; integrated circuit testing; logic testing; CMOS IC defects; IDDT testing; defect coverage; stuck open fault; switching; testable faults; transient current; CMOS integrated circuits; CMOS logic circuits; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Integrated circuit testing; Logic testing; Power supplies; Switching circuits;
Conference_Titel :
Test Symposium, 1997. (ATS '97) Proceedings., Sixth Asian
Conference_Location :
Akita
Print_ISBN :
0-8186-8209-4
DOI :
10.1109/ATS.1997.643986
