DocumentCode :
3221731
Title :
Reduced complexity SIMD-class architectures
Author :
Glover, Michael A. ; Rucinski, Andrzej ; Miller, W. Thomas
Author_Institution :
Current Technol., Durham, NH, USA
fYear :
1996
fDate :
9-11 Oct 1996
Firstpage :
352
Lastpage :
361
Abstract :
System engineering applied in leading microelectronic technologies requires novel computing architectures. These architectural counterparts of emerging technologies are expected to be dramatically different from existing architectural paradigms. To address this need, we are introducing a class of architectures which maintain computing robustness and reduced complexity in the interconnect domain, and still substantially differ from well established systolic systems. A class representative, a DRAM based system, is described in detail, with a permutation generation as an example of application
Keywords :
DRAM chips; memory architecture; parallel architectures; DRAM; SIMD computing architecture; complexity; interconnect; microelectronic technology; permutation generation; robustness; system engineering; Capacitors; Computer architecture; Hardware; Maintenance engineering; Microelectronics; Random access memory; Registers; Silicon; Systems engineering and theory; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Innovative Systems in Silicon, 1996. Proceedings., Eighth Annual IEEE International Conference on
Conference_Location :
Austin, TX
ISSN :
1063-2204
Print_ISBN :
0-7803-3639-9
Type :
conf
DOI :
10.1109/ICISS.1996.552442
Filename :
552442
Link To Document :
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