DocumentCode :
3221774
Title :
A register pressure sensitive instruction scheduler for dynamic issue processors
Author :
Silvera, Raúl ; Wang, Jian ; Gao, Guang R. ; Govindarajan, R.
Author_Institution :
Sch. of Comput. Sci., McGill Univ., Montreal, Que., Canada
fYear :
1997
fDate :
10-14 Nov 1997
Firstpage :
78
Lastpage :
89
Abstract :
Several modern superscalar processors contain an out-of-order (OOO) instruction issue mechanism, which resolves dependencies between instructions to expose greater instruction-level parallelism (ILP). How to extend a traditional instruction scheduler to take advantage of these hardware resources has presented both a challenge and an opportunity for compiler design. In this paper, we present a new approach for instruction scheduling, which reorders the instructions in a traditional instruction schedule to reduce its register pressure while maintaining the amount of ILP exploitable by the target OOO processor. This may prevent the introduction of spill code, thus producing a performance improvement. We have implemented our instruction scheduler under the MOST scheduling testbed. Our experiments show that the proposed approach reduces the register pressure by 12.81% in SPEC92 benchmark loops which do not require any spill code. For loops with a high register pressure, our approach reduced the amount of spill code required by an average of 32.08% and produced an average performance improvement of 8.79%
Keywords :
parallel processing; parallelising compilers; performance evaluation; processor scheduling; program control structures; storage allocation; MOST scheduling testbed; SPEC92 benchmark loops; compiler design; dynamic issue processors; instruction dependencies; instruction reordering; instruction-level parallelism; out-of-order instruction issue mechanism; performance improvement; register pressure-sensitive instruction scheduler; spill code; superscalar processors; Assembly; Degradation; Dynamic scheduling; Hazards; Marine vehicles; Processor scheduling; Registers; Scheduling algorithm; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel Architectures and Compilation Techniques., 1997. Proceedings., 1997 International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-8090-3
Type :
conf
DOI :
10.1109/PACT.1997.644005
Filename :
644005
Link To Document :
بازگشت