DocumentCode :
3221892
Title :
VLIW across multiple superscalar processors on a single chip
Author :
Kim, Soohong P. ; Hoare, Raymond R. ; Dietz, Henry G.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
fYear :
1997
fDate :
10-14 Nov 1997
Firstpage :
166
Lastpage :
175
Abstract :
Advances in IC technology increase the integration density for higher clock rates and provide more opportunities for microprocessor design. The authors propose a new paradigm to exploit instruction-level parallelism (ILP) across multiple superscalar processors on a single chip by taking advantages of both VLIW-style static scheduling techniques and dynamic scheduling of superscalar architecture. In the proposed paradigm, ILP is exploited by a compiler from a sequential program and this VLIW-like-parallelized code is further parallelized by 2-way superscalar engines at run-time. Superscalar processors are connected by an aggregate function network, which can enforce the necessary static timing constraints and provide appropriate inter-processor data communication mechanisms that are needed for ILP. The aggregate function operations are statically scheduled and implement not only fine-grain communication and control, but also simple global computations resembling systolic array operations within the network
Keywords :
microprocessor chips; parallelising compilers; pipeline processing; processor scheduling; systolic arrays; timing; VLIW-like parallelized code; VLIW-style static scheduling techniques; aggregate function network; chip; clock rates; compiler; dynamic scheduling; fine-grain communication; fine-grain control; global computations; instruction-level parallelism; integration density; inter-processor data communication mechanisms; microprocessor design; multiple superscalar processors; network; sequential program; static timing constraints; superscalar architecture; systolic array operations; two-way superscalar engines; Aggregates; Clocks; Dynamic scheduling; Engines; Microprocessors; Parallel processing; Processor scheduling; Program processors; Runtime; VLIW;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel Architectures and Compilation Techniques., 1997. Proceedings., 1997 International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-8090-3
Type :
conf
DOI :
10.1109/PACT.1997.644013
Filename :
644013
Link To Document :
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