DocumentCode :
3221950
Title :
Buffer-safe communication optimization based on data flow analysis and performance prediction
Author :
Fahringer, Thomas ; Mehofer, Eduard
Author_Institution :
Inst. of Software Technol. & Parallel Syst., Wien Univ., Austria
fYear :
1997
fDate :
10-14 Nov 1997
Firstpage :
189
Lastpage :
200
Abstract :
The paper presents a novel approach to reduce communication costs of programs for distributed memory machines. The techniques are based on uni-directional bit-vector data flow analysis that enable vectorizing and coalescing communication, overlapping communication with computation, eliminating redundant messages and amount of data being transferred both within and across loop nests. The data flow analysis differs from previous techniques that it does not require to explicitly model balanced communication placement and loops and does not employ interval analysis. The techniques are based on simple yet highly effective data flow equations which are solved iteratively for arbitrary control flow graphs. Moving communication earlier to hide latency has been shown to dramatically increase communication buffer sizes and can even cause run-time errors. The authors use P3T, a state-of-the-art performance estimator to create a buffer-safe program. By accurately estimating both the communication buffer sizes required and the implied communication times of every single communication of a program one can selectively choose communication that must be delayed in order to ensure a correct communication placement while maximizing communication latency hiding. Experimental results are presented to prove the efficacy of the communication optimization strategy
Keywords :
data flow analysis; distributed memory systems; performance evaluation; buffer-safe communication optimization; coalescing communication; communication buffer sizes; communication cost reduction; communication placement; computation; distributed memory machines; latency hiding; loop nests; performance estimator; performance prediction; redundant message elimination; uni-directional bit-vector data flow analysis; vectorizing communication; Algorithm design and analysis; Communication system control; Costs; Data analysis; Delay estimation; Equations; Flow graphs; Memory architecture; Performance analysis; Software performance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel Architectures and Compilation Techniques., 1997. Proceedings., 1997 International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-8090-3
Type :
conf
DOI :
10.1109/PACT.1997.644015
Filename :
644015
Link To Document :
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