DocumentCode :
3222039
Title :
Optimization of sampling method for overlay and alignment accuracy improvement
Author :
Jinseog Hong ; Junghyeon Lee ; Joonsoo Park ; Hanku Cho ; Jootae Moon
Author_Institution :
Semicond. R&D Center, Samsung Electron. Co. Ltd., Kyungki-Do, South Korea
fYear :
1999
fDate :
6-8 July 1999
Firstpage :
168
Lastpage :
169
Abstract :
The authors have investigated the sample plan dependency of global alignment repeatability and overlay measurement accuracy. To achieve better alignment repeatability is critical for improving not only in-wafer overlay but also wafer-to-wafer overlay control. Global alignment repeatability and its results are significantly affected by which chips in a wafer map are selected as global alignment use. Several sampling methods which are limited to symmetric group (translation, inversion, rotation symmetric) are tested.
Keywords :
integrated circuit measurement; integrated circuit testing; optimisation; sampling methods; alignment accuracy improvement; alignment repeatability; chips; global alignment repeatability; global alignment use; in-wafer overlay; optimization; overlay accuracy improvement; overlay measurement accuracy; sample plan dependency; sampling method; symmetric group; wafer map; wafer-to-wafer overlay control; Degradation; Moon; Noise robustness; Optimization methods; Reproducibility of results; Research and development; Sampling methods; Semiconductor device measurement; Semiconductor device noise; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microprocesses and Nanotechnology Conference, 1999. Digest of Papers. Microprocesses and Nanotechnology '99. 1999 International
Conference_Location :
Yokohama, Japan
Print_ISBN :
4-930813-97-2
Type :
conf
DOI :
10.1109/IMNC.1999.797530
Filename :
797530
Link To Document :
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