DocumentCode :
3222550
Title :
The Pesona16TM RISC 16-bit microprocessor-architecture, functional configurations, and performances
Author :
Rahman, Airul Azha Abd ; Rashid, Zainol Abidin Abdul ; Othman, Masuri
Author_Institution :
Microelectron. Lab., MIMOS Berhad, Malaysia
fYear :
2000
fDate :
2000
Firstpage :
139
Lastpage :
146
Abstract :
The first Malaysian made 16-bit RISC processor, the Pesona16TM, designed and developed by MIMOS is described in terms of its architecture, programming model and its functional capabilities. Performance analysis and comparison with other similar 16-bit processors in the market are also made
Keywords :
PLD programming; microprocessor chips; microprogramming; reduced instruction set computing; 16 bit; Pesona16 RISC microprocessor; RISC processor; architecture; functional capability; functional configurations; microprocessor architecture; performance analysis; programming model; Clocks; Computer architecture; Decoding; Functional programming; Laboratories; MIMO; Microelectronics; Microprocessors; Reduced instruction set computing; Registers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Semiconductor Electronics, 2000. Proceedings. ICSE 2000. IEEE International Conference on
Conference_Location :
Guoman Port Dickson Resort
Print_ISBN :
0-7803-6430-9
Type :
conf
DOI :
10.1109/SMELEC.2000.932452
Filename :
932452
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3222550
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