DocumentCode
3222679
Title
An efficient architecture of 8-bit CMOS analog-to-digital converter
Author
Tan, P.B.Y. ; Wagiran, R. ; Sidek, Roslina
Author_Institution
Dept. of Electr. & Electron. Eng., Putra Malasyia Univ., Serdang
fYear
2000
fDate
2000
Firstpage
178
Lastpage
186
Abstract
An 8-bit CMOS analog-to-digital converter (ADC) has been designed using a more efficient architecture. The simplified multistep 8-bit ADC requires two 4-bit full-flash cycles by using a modified 4-bit full-flash ADC with a voltage estimator. The speed of this new architecture is similar to conventional half-flash ADC but the die area consumption is much less due to reduced numbers of comparators and resistors
Keywords
CMOS integrated circuits; analogue-digital conversion; circuit CAD; comparators (circuits); integrated circuit design; resistors; 4 bit; 8 bit; CMOS ADC; CMOS ADC design; CMOS analog-to-digital converter; architecture speed; comparators; die area consumption; efficient architecture; full-flash cycles; half-flash ADC; modified full-flash ADC; resistors; voltage estimator; Analog-digital conversion; Decoding; Design engineering; Notice of Violation; Phase change materials; Resistors; Signal processing; Signal resolution; Signal to noise ratio; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Electronics, 2000. Proceedings. ICSE 2000. IEEE International Conference on
Conference_Location
Guoman Port Dickson Resort
Print_ISBN
0-7803-6430-9
Type
conf
DOI
10.1109/SMELEC.2000.932459
Filename
932459
Link To Document