A design for software defined M-PSK radio on FPGA for low SNRs and symbol rates upto 10MS/s

In this paper we present an architecture for a software defined M-PSK (M=2, 4, 8) receiver which was prototyped to handle real world satellite signals of E_b/N₀ up to 4dB for BPSK and QPSK and up to 6dB for 8-PSK using only 2 samples per symbol. This design supports symbol rates between 32kS/s and 10MS/s. We also present the BER curves of the demodulator designed and the approach we took to obtain them. This infrastructure is scalable to any kind of real time software radio development and aids rapid development on FPGA.