Baseband MIMO receiver architecture for MC-CDMA and its FPGA implementation

A baseband multi-input, multi-output (MIMO) multi-carrier code division multiple access (MC-CDMA) downlink system meeting wideband CDMA (WCDMA) bandwidth requirements is simulated and its receiver part is implemented into a field programmable gate array (FPGA). The receiver was designed by integrating an existing single-input, single-output (SISO) fixed-point MC-CDMA receiver with an existing floating-point MIMO receiver. The receiver employs temporal multiplexing in order to use a single Vertical Bell Laboratories LAyered Space-Time (V-BLAST) detector. Simulation results of a complete MIMO MC-CDMA system show improvements over the SISO case. Implementation results show that it is possible to implement this receiver design into a single FPGA device.