DocumentCode
3223517
Title
An optimized architecture of cascaded crossbar switches in SoC systems
Author
Jiuchong, Niu ; Xin, Wang ; Qingwang, Lu ; Ziyi, Hu
Author_Institution
Shenzhen Grad. Sch., Key Lab. of Integrated Microsyst. Sci. & Eng. Applic., Peking Univ., Shenzhen, China
fYear
2009
fDate
25-27 Dec. 2009
Firstpage
178
Lastpage
181
Abstract
For high frequency design of SoC systems, cascaded crossbar switches become more and more popular. In this paper, we present a method based on FFT-butterfly architecture. This method can provide optimal topology of cascaded crossbar switches, which consists of multiple small crossbar switches. We apply it to AMBA3 AXI-based bus system design. Experimental results show that the proposed methods allow SoC designs with higher performance, with a reduction to area by 16.6%.
Keywords
fast Fourier transforms; network topology; system buses; system-on-chip; AMBA3 AXI-based bus system design; FFT-butterfly architecture; cascaded crossbar switches; system-on-chip; Switches; FFT-butterfly architecture; SoC; cascaded crossbar switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of
Conference_Location
Xi´an
Print_ISBN
978-1-4244-4297-3
Electronic_ISBN
978-1-4244-4298-0
Type
conf
DOI
10.1109/EDSSC.2009.5394160
Filename
5394160
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