DocumentCode
3223572
Title
Capital productivity-challenge and opportunity
Author
Rowe, William
Author_Institution
IBM Corp., Essex Junction, VT, USA
fYear
1995
fDate
13-15 Nov 1995
Firstpage
23
Abstract
Summary form only given. Controlling the rapidly increasing costs of semiconductor wafer fabricators presents a serious challenge to the semiconductor industry. SEMATECH, in cooperation with its members and SEMI/SEMATECH suppliers has developed a methodology to maintain the historic price per function decline rate for semiconductor products. A series of 0.25 micron generation fab cost models were developed at SEMATECH. The models incorporated advanced logic and DRAM processes, operational and financial inputs and equipment cost and performance goals. Wafer processing costs from the model were compared to affordable costs developed by the SEMATECH Competitive Analysis Group. The result of this process has been a set of mutually agreed upon cost and performance targets for the 0.25 micron generation of equipment. Equipment meeting those targets will be more cost effective than that currently available. High operating efficiency as measured by overall equipment effectiveness (OEE) is essential to achieving improved capital productivity goals.
Keywords
costing; economics; human resource management; semiconductor device manufacture; 0.25 micron; DRAM processes; SEMATECH Competitive Analysis Group; capital productivity; cost models; logic processes; overall equipment effectiveness; semiconductor industry; semiconductor wafer fabricators; Costs; Electronics industry; Logic; Meetings; Microelectronics; Productivity; Random access memory; Semiconductor device manufacture; Semiconductor device modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Semiconductor Manufacturing Conference and Workshop, 1995. ASMC 95 Proceedings. IEEE/SEMI 1995
ISSN
1078-8743
Print_ISBN
0-7803-2713-6
Type
conf
DOI
10.1109/ASMC.1995.484332
Filename
484332
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