Title :
Test pattern generation for combinatorial multi-valued networks based on generalized D-algorithm
Author :
Shmerko, Vlad P. ; Yanushkevich, S. ; Levashenko, V.
Author_Institution :
Inst. of Comput. Sci. & Inf. Syst., Tech. Univ. Szczecin, Poland
Abstract :
A calculus for test pattern generation for Multi-Valued Logic (MVL) networks using so-called Direct D-cubes (DD-cubes) is proposed. The concept of the DD-cubes is introduced based on Direct Logic Derivatives generated by a matrix algorithm. It provides a means to support the central stages of test generating on parallel hardware, for instance, linear systolic arrays
Keywords :
combinational circuits; logic testing; multivalued logic; multivalued logic circuits; Direct D-cubes; Direct Logic Derivatives; MVL; linear systolic arrays; matrix algorithm; multi-valued networks; parallel hardware; test generating; test pattern generation; Calculus; Circuit faults; Circuit testing; Computer science; Electrical fault detection; Fault detection; Information systems; Logic testing; Systolic arrays; Test pattern generators;
Conference_Titel :
Multiple-Valued Logic, 1997. Proceedings., 1997 27th International Symposium on
Conference_Location :
Antigonish, NS
Print_ISBN :
0-8186-7910-7
DOI :
10.1109/ISMVL.1997.601388
