Title :
A novel ESD power clamp circuit with TSPCL D flip-flop
Author :
Tang, Baojun ; Liu, Hongxia
Author_Institution :
Sch. of Microelectron., Xidian Univ., Xi´´an, China
Abstract :
In order to protect the internal circuit effectively, the design of ESD clamp protection circuit becomes more important. In this paper, a novel ESD power clamp circuit for 0.18 ¿m CMOS process is proposed. The new clamp circuit uses the edge triggering TSPCL D flip-flop to turn on and time delay. By adding the leakage transistor of small size, the circuit can turn off effectively. It has the advantage of dynamic transmission structure as well. The results show that the clamp circuit can reduce the false triggering and power supply noise.
Keywords :
CMOS logic circuits; electrostatic discharge; flip-flops; power supply circuits; CMOS process; TSPCL flip flops; edge triggering D flip-flop; electrostatic discharge power clamp circuit; false triggering reduction; leakage transistor; power supply noise; size 0.18 mum; Circuits; Clamps; Costs; Delay effects; Detectors; Electrostatic discharge; Event detection; Flip-flops; MOS devices; Protection; ESD (Electronic Static Discharge); TSPCL; clamp circuit; turn-off mechanism;
Conference_Titel :
Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of
Conference_Location :
Xi´an
Print_ISBN :
978-1-4244-4297-3
Electronic_ISBN :
978-1-4244-4298-0
DOI :
10.1109/EDSSC.2009.5394176
