Title :
A novel SOI IGBT for Power-Rail ESD clamp circuit
Author :
Zhu, Jing ; Qian, Qinsong ; Sun, Weifeng
Author_Institution :
Nat. ASIC Syst. Eng. Res. Center, Southeast Univ., Nanjing, China
Abstract :
A novel and robust transient-assisted high voltage SOI (Silicon On Insulator) IGBT (Insulated Gate Bipolar Transistor) with a parasitic capacitance for Power-Rail ESD clamp circuit in power integrated circuits is proposed in this work. Without using any other external trigger circuits, the triggering voltage of the improved device reduces by 13% in comparison with the conventional device structure under the 2ns rise time TLP (Transmission Line Pulsing) stress condition. Moreover, the proposed device is not sensitive to the normal VDD power-on transition event (with a rise time in milliseconds) because the parasitic capacitance is very small. The behavior of the novel device structure has been studied by simulations and verified by experiment.
Keywords :
capacitance; electrostatic discharge; insulated gate bipolar transistors; power bipolar transistors; silicon-on-insulator; transmission lines; TLP stress condition; high voltage SOI IGBT; insulated gate bipolar transistor; parasitic capacitance; power integrated circuits; power-on transition event; power-rail ESD clamp circuit; silicon on insulator; time 2 ns; transmission line pulsing stress condition; Clamps; Electrostatic discharge; Insulated gate bipolar transistors; Parasitic capacitance; Power integrated circuits; Power transmission lines; Robustness; Silicon on insulator technology; Trigger circuits; Voltage; Silicon On Insulator (SOI); Transmission Line Pulsing (TLP); electrostatic discharge (ESD); lateral insulated gate bipolar transistor (IGBT); transient-assisted;
Conference_Titel :
Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of
Conference_Location :
Xi´an
Print_ISBN :
978-1-4244-4297-3
Electronic_ISBN :
978-1-4244-4298-0
DOI :
10.1109/EDSSC.2009.5394178
