A novel SOI IGBT for Power-Rail ESD clamp circuit

A novel and robust transient-assisted high voltage SOI (Silicon On Insulator) IGBT (Insulated Gate Bipolar Transistor) with a parasitic capacitance for Power-Rail ESD clamp circuit in power integrated circuits is proposed in this work. Without using any other external trigger circuits, the triggering voltage of the improved device reduces by 13% in comparison with the conventional device structure under the 2ns rise time TLP (Transmission Line Pulsing) stress condition. Moreover, the proposed device is not sensitive to the normal V_DD power-on transition event (with a rise time in milliseconds) because the parasitic capacitance is very small. The behavior of the novel device structure has been studied by simulations and verified by experiment.