Title :
Power rail ESD circuit simulation and verification
Author :
Zhiguo, Li ; Suge, Yue ; Yongshu, Sun
Author_Institution :
Beijing Microelectron. Technol. Inst., Beijing, China
Abstract :
In order to advance the performance of the ESD circuit for the power rail protection, a kind of design scheme named GDNMOS (Gate Driven NMOS) is studied in this paper. NMOS, inverter and RC couple cell are the makeup in this scheme. Device simulation in a pre_Si phase will be an economical way. NMOS parameters are optimized in a device simulation way firstly. By discharge time study the RC-time is ascertained to differentiate ESD or not. And short delay is achieved by appropriate inverter design. This scheme with optimized parameters, not only the turn on speed is accelerated, but also better transparency is achieved. Turn on uniformity of the NMOS is also enhanced by this scheme. The design is verified in a 0.18 um salicided CMOS process finally.
Keywords :
CMOS integrated circuits; invertors; network synthesis; CMOS process; RC couple cell; Si; gate driven NMOS; inverter design; power rail ESD circuit simulation; size 0.18 mum; Acceleration; Circuit simulation; Coupling circuits; Delay; Electrostatic discharge; Inverters; MOS devices; Power generation economics; Protection; Rails; ESD; GDNMOS; Simulation; TLP;
Conference_Titel :
Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of
Conference_Location :
Xi´an
Print_ISBN :
978-1-4244-4297-3
Electronic_ISBN :
978-1-4244-4298-0
DOI :
10.1109/EDSSC.2009.5394179
