Dynamic and short-circuit power of CMOS gates driving lossless transmission lines

Author

Ismail, Yehea I. ; Friedman, Eby G. ; Neves, Jose L.

Author_Institution

Dept. of Electr. Eng., Rochester Univ., NY, USA

fYear

1998

fDate

19-21 Feb 1998

Firstpage

39

Lastpage

44

Abstract

The dynamic and short-circuit power consumption of a CMOS gate driving an LC transmission line as a limiting case of an RLC transmission line is investigated in this paper. Closed form solutions for the output voltage and short-circuit power of a CMOS gate driving an LC transmission line are presented These solutions agree with AS/X circuit simulations within 11% error for a wide range of transistor widths and line impedances. The ratio of the short-circuit to dynamic power is shown to be less than 7% for CMOS gates driving LC transmission lines where the line is matched or underdriven. The total power consumption is expected to decrease as inductance effects become more significant as compared to an RC dominated interconnect

Keywords

CMOS logic circuits; circuit analysis computing; inductance; integrated circuit modelling; logic CAD; logic gates; transmission lines; AS/X circuit simulations; CMOS gates; LC transmission line; closed form solutions; dynamic power; inductance effects; line impedances; lossless transmission lines; output voltage; power consumption; short-circuit power; transistor widths; Capacitors; Circuit simulation; Closed-form solution; Distributed parameter circuits; Energy consumption; Impedance; Inductance; Integrated circuit interconnections; Microelectronics; Power transmission lines; Propagation losses; RLC circuits; Superconducting transmission lines; Voltage; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on

Conference_Location

Lafayette, LA

ISSN

1066-1395

Print_ISBN

0-8186-8409-7

Type

conf

DOI

10.1109/GLSV.1998.665197

Filename

665197