Computer aided test synthesis for a parallel scan design of finite state sequential machines

Author

Iyengar, S.N. ; Dandapani, R. ; Reddy, S.M.

Author_Institution

Dept. of Electr. Eng., Colorado Univ., Colarado Springs, CO, USA

fYear

1988

fDate

21-23 March 1988

Firstpage

152

Lastpage

156

Abstract

A parallel scan design for finite-state machines (FSMs) was proposed by S.M. Reddy and R. Dandapani (1987), and analyzed for critical parameters such as area, delay, and active devices. The authors study the design presented by Reddy and Dandapani for test parameters including increase in test vectors for both cross-point and single stuck-at faults, fault coverage, and time taken for fault detection. It is shown that even though there is an increase in the number of test vectors due to additional hardware, the testing time is reduced to the parallelism of the design. NMOS technology is used in the analysis.<>

Keywords

logic CAD; logic testing; sequential circuits; sequential machines; NMOS technology; active devices; area; computer aided test synthesis; delay; fault coverage; fault detection; finite state sequential machines; parallel scan design; test parameters; test vectors; testing time; Circuit faults; Circuit testing; Concurrent computing; Hardware; MOS devices; Parallel processing; Programmable logic arrays; Redundancy; Sequential analysis; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'

Conference_Location

Colorado Springs, CO, USA

Type

conf

DOI

10.1109/REG5.1988.15920

Filename

15920