A hybrid CMOS-SET multiplier using frequency modulation

This paper proposes a hybrid CMOS-SET multiplier, which adopts frequency modulation technique in order to fully utilize SET´s unique Coulomb blockade oscillation characteristics. With advantages of the hybrid architecture, the multiplication result of two digital inputs is first modulated in frequency domain, and then converted into a digital output with the help of PLL and ADC components. As the circuit operation is performed with periodic oscillating signals instead of particular voltages or charges, the proposed multiplier exhibits the high immunity against background charge fluctuation and temperature variation. The structure can also be used to build a large multiplier in order to overcome the limitations of large gate capacitances required for SET devices.