Title :
Monitoring VLSIC fabrication processes: a Bayesian approach
Author :
Rao, Suraj ; Strojwas, Andrzej ; Lehoczky, John ; Schervish, Mark
Author_Institution :
Dept. of Stat., Carnegie Mellon Univ., Pittsburgh, PA, USA
Abstract :
We have developed a process monitoring system, in a Bayesian framework, which is designed to be used for monitoring VLSIC and other multi-stage manufacturing processes. For a single step process, the Bayesian monitor is at least as good as the Shewhart-CUSUM combination charts for detecting changes in the distribution of the in-lines collected from the step. For a multi-stage process, however, the Bayesian monitor can significantly reduce the detection time by using in-line correlation information from earlier stages.
Keywords :
Bayes methods; VLSI; integrated circuit technology; semiconductor process modelling; Bayesian method; Shewhart-CUSUM combination chart; VLSIC fabrication; in-line correlation; multi-stage manufacturing; process monitoring; Additive noise; Bayesian methods; Computerized monitoring; Condition monitoring; Control charts; Fabrication; Predictive models; Semiconductor device modeling; Statistics; Uncertainty;
Conference_Titel :
Advanced Semiconductor Manufacturing Conference and Workshop, 1995. ASMC 95 Proceedings. IEEE/SEMI 1995
Print_ISBN :
0-7803-2713-6
DOI :
10.1109/ASMC.1995.484375