FIR filter design based on retiming automation using VLSI design metrics

Finite Impulse Response (FIR) Filter can be designed by formulation of specifications which are for a particular application requirement. In this paper, an efficient FIR filter is designed using register minimization retiming technique. Also, an optimization environment is designed such that filter components of post retimed circuit such as adder and multiplier are upgraded depending on the VLSI design metrics such as area, speed or power as according to designer´s need and synthesizable code in Hardware Description Language [HDL] is generated. Retiming is a technique in which alteration to the critical path of FIR filter is done by changing the placement of the registers in the original FIR filter circuit. The placement of registers has to be made such that the functionality is not altered and critical path is minimized. The critical path minimization reduces overall clock period thereby increasing the clock frequency in retiming. At times, this may lead to increased register counts. The register minimization retiming provides the best compromise of clock period and register count. The FIR filter which needs to be optimized can be given to the optimization environment either as data flow graph or as a matrix. The designed optimization environment performs register minimization retiming and generates the synthesizable HDL of filter circuit. Also, different adders and multipliers are designed and their VLSI design metrics are compared in this work. Based on this comparison, adder and multiplier for a particular performance parameter such as area, power or delay is identified. A GUI is designed with Nokia QT for binding retimed FIR filter with efficient adder and multiplier components. Hence using register minimization retiming and component binding based on VLSI design metrics, an optimized digital FIR filters can be designed with minimum design cycle time.