Title :
Research of SBB effect on SOI-MOSFET low power 4T SRAM cell
Author :
Ma, Zhuang ; Yu, Siehen ; Shao, Zhibiao
Author_Institution :
Dept. of Microelectron., Xi´´an Jiaotong Univ., Xi´´an, China
Abstract :
A high drive current and low power 4T SOI-SRAM cell with 0.5 V supply voltage is proposed. This structure adopts Cross-shaped gate n-MOSFET and ultra thin self-body-bias (SBB) resistor. They share the same gate electrode to form the inverter of SRAM cell. The cross-shaped gate n-MOSFET increases the drive current. Furthermore, the process of SBB resistor is simple and compatible with SOI-CMOS process. The performance and process of the proposed memory cell are simulated by MEDICI and T-SUPREM4. Results show that the ultra thin SBB resistor has a 4.1 × 104 on/off-state current ratio and its on-state current closed to 10 uA/um is comparable to the n-MOSFET. At 0.5 V supply voltage, the memory cell´s static noise margin (SNM) is about 296 mV and the dynamic power dissipation of write and read operation are about 1.6 uW and 1.2 uW respectively.
Keywords :
MOSFET; SRAM chips; elemental semiconductors; silicon-on-insulator; thin film resistors; SOI-CMOS process; SOI-MOSFET low power 4T SRAM cell; Si; cross-shaped gate n-MOSFET; dynamic power dissipation; gate electrode; high drive current; memory cell static noise margin; on-off state current ratio; on-state current; read operation; ultrathin self-body-bias resistor; voltage 0.5 V; write operation; Biomedical electrodes; Integrated circuit noise; Inverters; MOSFET circuits; Medical simulation; Power dissipation; Random access memory; Read-write memory; Resistors; Voltage; 4T SRAM; Cross-shaped gate; SBB; SOI; on/off-state current ratio;
Conference_Titel :
Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of
Conference_Location :
Xi´an
Print_ISBN :
978-1-4244-4297-3
Electronic_ISBN :
978-1-4244-4298-0
DOI :
10.1109/EDSSC.2009.5394218
