ELsim: a timing simulator for digital CMOS integrated circuits

Author

Malowany, M.E. ; Malowany, A.S.

Author_Institution

Comput. Vision & Robotics Lab., McGill Res. Center for Intelligent Machines, Montreal, Que., Canada

fYear

1989

fDate

1-2 June 1989

Firstpage

616

Lastpage

619

Abstract

The basic operating principles of ELsim, a timing simulator for digital CMOS circuits, are discussed. ELsim uses the electrical-logic, or ELogic, method where time is solved for rather than voltage and an event-driven, selective trace approach is used which exploits circuit latency to improve simulation speed. Voltage levels at the circuit nodes are descretized, and the size of the voltage steps can be increased to trade accuracy for simulation speed. Results of a comparison of the ELsim simulator performance to that of SPICE for sample CMOS circuits are featured. In general, the delay times and waveforms calculated with ELsim show satisfactorily agreement with those obtained using SPICE.<>

Keywords

CMOS integrated circuits; circuit CAD; circuit analysis computing; digital integrated circuits; digital simulation; ELogic; ELsim; SPICE; circuit latency; circuit nodes; delay times; digital CMOS integrated circuits; electrical-logic; event driven approach; selective trace approach; simulation speed; timing simulator; waveforms; CMOS digital integrated circuits; CMOS integrated circuits; Capacitors; Circuit simulation; Circuit testing; Computational modeling; Computer simulation; SPICE; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Computers and Signal Processing, 1989. Conference Proceeding., IEEE Pacific Rim Conference on

Conference_Location

Victoria, BC, Canada

Type

conf

DOI

10.1109/PACRIM.1989.48439

Filename

48439