Title :
Process integrated of high aspect ratio copper dual damascene process
Author_Institution :
Dept. of Technol. Manage., Leader Univ., Tainan, Taiwan
Abstract :
The performance of the manufacturing process in semiconductor determines the overall manufacturability of the process. It has been known that pattern missing and defects could be prevented by optimal the process module tuning. The abnormal pattern collapse observed in this process and numerous defects could be prevented by optimizing the fabrication process module tuning. To successfully integrated sub-micron dual damascene process with good electrical and reliability performance after process improvement of lithography patterning, etch and dual damascene cleaning on semiconductor wafer fabrication processes were included.
Keywords :
copper; etching; integrated circuit interconnections; lithography; reliability; Cu; dual damascene cleaning; electrical performance; etching; fabrication process module tuning; high aspect ratio copper dual damascene process; lithography patterning; reliability; semiconductor wafer fabrication processes; submicron dual damascene process; Cleaning; Copper; Etching; Fabrication; High speed integrated circuits; Integrated circuit interconnections; Plasma applications; Plasma devices; Plasma materials processing; Resists; Aspect Ratio; BEOL; Copper Dual Damascene; Process Integration;
Conference_Titel :
Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of
Conference_Location :
Xi´an
Print_ISBN :
978-1-4244-4297-3
Electronic_ISBN :
978-1-4244-4298-0
DOI :
10.1109/EDSSC.2009.5394250
