An optimized design for a decimation filter and implementation for Sigma-Delta ADC

The area, speed, and power consumption of over-sampled data converters are governed largely by the decimation filters in Sigma-Delta Analog/Digital converters(ADC) and multiplication is the core operation of the digital filter, so the performance of digital system is determined by multiplication. This paper compares four different popular methods: Conventional multiplications and additions; full custom distributed arithmetic (DA) scheme; Add-and-Shift method with CSD encoding; advanced sub-expression sharing algorithm. Each scheme is analyzed in detail including implementing process and the experimental results are given to evaluate each scheme. All of these implementations are aimed to implement using Design Compiler. Then this paper presents an optimized circuit for the decimation filter and the decimation filter for Sigma-Delta ADC is implemented using 0.35 ¿m CMOS technology, with an approximate silicon area of 19 mm.