DocumentCode
3225687
Title
Validation of reactive embedded systems against temporal requirements
Author
Strug, Joanna ; Deniziak, Stanislaw ; Sapiecha, Krzysztof
Author_Institution
Cracow Univ. of Technol., Krakow, Poland
fYear
2004
fDate
24-27 May 2004
Firstpage
152
Lastpage
159
Abstract
Efficient methods of automatic generation of test scenarios to validate a system against functional requirements have already been developed. However, there are no such satisfactory methods as far as temporal requirements are concerned. A method of automatic generation of test scenarios for verification of time constraints for reactive embedded systems is presented.
Keywords
automatic test pattern generation; embedded systems; formal specification; formal verification; logic testing; systems analysis; temporal logic; automatic test scenario generation; functional requirements; reactive embedded system validation; temporal requirements; time constraint verification; Automatic testing; Design methodology; Electronic mail; Embedded system; Formal verification; Logic; Performance analysis; Real time systems; System testing; Time factors;
fLanguage
English
Publisher
ieee
Conference_Titel
Engineering of Computer-Based Systems, 2004. Proceedings. 11th IEEE International Conference and Workshop on the
Print_ISBN
0-7695-2125-8
Type
conf
DOI
10.1109/ECBS.2004.1316694
Filename
1316694
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