• DocumentCode
    3225693
  • Title

    Reduced-latency scheduling scheme for min-max non-binary LDPC decoding

  • Author

    Zhang, Xinmiao ; Cai, Fang

  • fYear
    2010
  • fDate
    6-9 Dec. 2010
  • Firstpage
    414
  • Lastpage
    417
  • Abstract
    Compared to binary low-density parity-check (LDPC) codes, non-binary (NB) LDPC codes can achieve higher coding gain when the code length is moderate. On the other hand, the decoding of NB-LDPC codes is more complicated since a vector of messages instead of a single message is passed along each edge of the associated Tanner graph. Layered decoding can be employed to simplify LDPC decoding. However, there is extra latency between the decoding of layers caused by check node processing, message permutation and updating when applied to NB-LDPC codes. In this paper, a novel scheduling scheme is developed to eliminate the extra latency for the Min-max decoding of quasi-cyclic (QC) NB-LDPC codes using trellis-based check node processing. Assume that each row of sub-matrices in the parity check matrix of a QCNB-LDPC code is divided into two layers, the proposed scheme can reduce the decoding latency by a factor of around (2dc + 5)/2dc, where dc is the check node degree. It leads to significant speedup when dc is not large. Moreover, the area overhead of the proposed scheme is less than 10%.
  • Keywords
    cyclic codes; parity check codes; scheduling; trellis codes; NB-LDPC codes; Tanner graph; layered decoding; low density parity check; min-max decoding; parity check matrix; quasi-cyclic codes; reduced latency scheduling scheme; trellis based check node processing; Clocks; Computer architecture; Decoding; Multiplexing; Parity check codes; Registers; Sorting;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on
  • Conference_Location
    Kuala Lumpur
  • Print_ISBN
    978-1-4244-7454-7
  • Type

    conf

  • DOI
    10.1109/APCCAS.2010.5774734
  • Filename
    5774734