Analogue design issues for SOI CMOS

There are many issues facing the analogue designer for mainstream VLSI SOI CMOS. Some are improvements (more useable bandwidth, less crosstalk), but many are difficulties. Thermal behaviour does not depend very strongly on the technology roadmap but possible matching problems do. The presence and degree of floating body behaviour hinges on specific process architecture as well as device layout. Except for kink effect coincident with saturation, most of these factors can be largely accommodated in design provided that the circuit level models and their extracted parameters are adequate. Without these, design becomes uncertain and requires time-consuming iterations incompatible with modern practices