1.8 V CMOS low noise CPPLL design

This paper describes a design of a low noise Charge Pump PLL. The design utilizes a top-down methodology to determine system parameters. Using the behavioral simulation, the performance of the PLL system is verified. The PLL circuit design is based on 0.18 um CMOS process and its supply voltage is 1.8 V.The PLL has an input clock frequency of 12 MHz and an output clock frequency of 480 MHz with eight phases. According to the measurement the cycle-to-cycle jitter of the output clock at 480 Mhz is only 60 ps peak-to-peak, the long term jitter is 90 ps. Moreover, the maximum lock time is about 6 us and the maximum frequency overshot is about 13%, power dissipation is 7.2 mW. The testing results prove precision of behavioral simulation.