Stochastic TDC architecture with self-calibration

Author

Ito, Satoshi ; Nishimura, Shigeyuki ; Kobayashi, Haruo ; Uemori, Satoshi ; Tan, Yohei ; Takai, Nobukazu ; Yamaguchi, Takahiro J. ; Niitsu, Kiichi

Author_Institution

Dept. of Electron. Eng., Gunma Univ., Kiryu, Japan

fYear

2010

fDate

6-9 Dec. 2010

Firstpage

1027

Lastpage

1030

Abstract

This paper describes a time-to-digital converter (TDC) architecture with fine time resolution, self-calibration and self-testing, and these features are realized by the following: (1) Encoder circuit that ensures monotonic characteristics. (2) Self-calibration circuit for linearity improvement. (3) Stochastic architecture for fine time resolution. (4) Self-testing for reliability requirements. These features can be implemented with an advanced fine CMOS process using digital design methodology. The circuit structure and operation are described, and MATLAB simulation results are presented.

Keywords

calibration; circuit CAD; convertors; encoding; reliability; MATLAB simulation; advanced fine CMOS process; circuit structure; digital design methodology; encoder circuit; fine time resolution; linearity improvement; monotonic characteristics; reliability requirement; self-calibration circuit; self-testing; stochastic TDC architecture; stochastic architecture; time-to-digital converter architecture; Built-in self-test; Calibration; Delay; Delay lines; Histograms; Linearity; Simulation; Self-Calibration; Self-Testing; Stochastic TDC; TDC;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on

Conference_Location

Kuala Lumpur

Print_ISBN

978-1-4244-7454-7

Type

conf

DOI

10.1109/APCCAS.2010.5774740

Filename

5774740