Data wordlength reduction in 90nm multipliers

Digital signal processing applications need complex arithmetic functions for implementing filters and real time statistical operations. Power consumption in these systems directly relies on their multipliers precision, as a bigger bitwidth will result in higher active power figures. On the other hand, the resolution of the signal processing block also relies on the multiplier precision, where lowering the bitwidth will result in less accuracy. This dilemma becomes specially problematic in portable devices where the optimum equilibrium needs to be found in order to get acceptable results with the longest possible battery life. An ASIC based configurable approach where the multiplier bitwidth can be modified at runtime is presented in this paper. It allows the accuracy of the output to be dynamically reduced or extended, in order to get power-related benefits, as the dynamic power consumption can be optimized to the application needs. This paper presents new results on applying this technique to a Wallace tree-based multiplier synthesized in 90 nm using standard cell libraries.