Atto-Joule gates for the whole voltage range

Reducing the supply voltage is by far the most widely used low-power technique, as reducing dynamic power quadratically and leakage power linearly, while sacrificing on performances. A similar but less explored route is to reduce and/or limit currents (instead of reducing voltages), e.g., through transistor sizing. This paper details a comparison of a reverse-sized CMOS scheme (which reduces currents), with both a classical CMOS implementation and an ultra low power (ULP) sub-threshold CMOS scheme. Simulation results show that the reverse-sized CMOS inverter performs well over the whole range of supply voltages: (i) it dissipates significantly less than a classical CMOS inverter (20-60×), while it does degrade performances (5-20×) but less than power gaining, i.e., not proportionally; (ii) it is much faster (100-200×) than a ULP inverter, at moderately larger power consumptions (10-40×), but again less than proportional; and (iii) its power-delay-product (PDP) is constantly 5-8× lower than that of the other two inverters considered over the whole range of supply voltages. In particular, a reverse-sized CMOS inverter in 16nm at 300mV has a delay of 9.16ns while breaking the atto-Joule barrier (0.906aJ).