A new SOI inverter for low power applications

The speed degradation in CMOS circuits with the supply voltage reduction is an important obstacle in the scale down of supply voltage. Thus, many attempts to reduce the gate delay have been tried using the dynamic threshold scheme. However, they have limitations in the operation voltage and large leakage current. We propose a new type of SOI inverter gate which has considerably shortened circuit delay with similar energy consumption in the conventional SOI CMOS circuit at low voltage operation. It uses the positive-body bias effect that enhances drain currents when the body is biased positively. The operation principle of the proposed gate, the optimal circuit and device conditions studied by simulations, and the fabrication and measurement data are reported in this paper