Narrow-width design methodology for operational amplifiers in SOI technology

Summary form only given. In this paper, a narrow-width methodology (NWM) for designing analog gain stages in SOI technology is presented. By employing NWM, we can, achieve better circuit performance in SOI when compared with bulk CMOS. Given the same testing conditions for both bulk and SOI 2-stage Miller compensated op amp, our study showed a 2X+ speed improvement and a 2X+ reduction of compensation capacitance in SOI. With a judicious choice of transistor sizes, one can also exploit the speed advantages of SOI circuits over bulk in other op amp topologies such as folded-cascode