Narrow-width design methodology for operational amplifiers in SOI technology

Author

Cheung, Denny T Y ; Lau, Jack ; Fung, Samuel K H ; Chan, Philip C.H.

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Clear Water Bay, Hong Kong

fYear

1996

fDate

30 Sep-3 Oct 1996

Firstpage

22

Lastpage

23

Abstract

Summary form only given. In this paper, a narrow-width methodology (NWM) for designing analog gain stages in SOI technology is presented. By employing NWM, we can, achieve better circuit performance in SOI when compared with bulk CMOS. Given the same testing conditions for both bulk and SOI 2-stage Miller compensated op amp, our study showed a 2X+ speed improvement and a 2X+ reduction of compensation capacitance in SOI. With a judicious choice of transistor sizes, one can also exploit the speed advantages of SOI circuits over bulk in other op amp topologies such as folded-cascode

Keywords

CMOS analogue integrated circuits; capacitance; integrated circuit design; operational amplifiers; silicon-on-insulator; CMOS op amp design; Miller compensated op amp; SOI technology; Si; analog gain stages; compensation capacitance reduction; narrow-width design methodology; operational amplifier design; speed improvement; Design engineering; Design methodology; Electron devices; Low power electronics; MOSFET circuits; Notice of Violation; Operational amplifiers; Power engineering and energy; Solid state circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 1996. Proceedings., 1996 IEEE International

Conference_Location

Sanibel Island, FL

ISSN

1078-621X

Print_ISBN

0-7803-3315-2

Type

conf

DOI

10.1109/SOI.1996.552474

Filename

552474