DocumentCode :
3227139
Title :
N3asic-based nanowire volatile RAM
Author :
Rahman, Mostafizur ; Narayanan, Pritish ; Moritz, Csaba Andras
Author_Institution :
Univ. of Massachusetts, Amherst, MA, USA
fYear :
2011
fDate :
15-18 Aug. 2011
Firstpage :
1097
Lastpage :
1101
Abstract :
As CMOS technology advances into the nanoscale, the continuous push for low power, high performance, and dense volatile memory is reaching its limit. Moreover, in the nanometer regime complex design rules and manufacturing costs are escalating as it is getting increasingly difficult to control manufacturing process parameters. In this paper, we propose a novel 10 transistor based volatile Nanowire Random Access Memory (10T-NWRAM) which is highly scalable and manufacturing friendly since it is based on the very regular N3ASIC fabric. Besides, it has the potential to be significantly faster and low leakage alternative to SRAM since high performance nanowire FETs and dynamic logic is used for memory architecture.
Keywords :
CMOS integrated circuits; field effect transistors; integrated circuit design; nanowires; random-access storage; 10 transistor based volatile nanowire random access memory; CMOS technology; N3 ASIC-based nanowire volatile RAM; dense volatile memory; dynamic logic; high performance nanowire FET; manufacturing costs; manufacturing process parameter control; memory architecture; nanometer regime complex design rules; nanoscale; CMOS integrated circuits; Computer architecture; Fabrics; Logic gates; Manufacturing; Random access memory; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Nanotechnology (IEEE-NANO), 2011 11th IEEE Conference on
Conference_Location :
Portland, OR
ISSN :
1944-9399
Print_ISBN :
978-1-4577-1514-3
Electronic_ISBN :
1944-9399
Type :
conf
DOI :
10.1109/NANO.2011.6144449
Filename :
6144449
Link To Document :
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