An optimized ΔΣ modulator in fractional-N frequency synthesizer for UHF RFID reader

Author

Shi, Chunqi ; Zhang, Runxi ; Chen, Lei ; Lai, Zongsheng

Author_Institution

East China Normal Univ., Shanghai, China

fYear

2010

fDate

8-11 May 2010

Firstpage

1468

Lastpage

1471

Abstract

A 3rd-order 3-bit single-loop ΔΣ modulator in fractional-N frequency synthesizer for UHF RFID Reader is optimized in terms of phase noise. Feed forward and feedback path structure is proposed in the ΔΣ modulator. The location of zeros and poles are placed at desired frequency for noise shaping by configuring feed forward and feedback coefficients. A fully integrated ΔΣ fractional-N frequency synthesizer with digital ΔΣ modulator is implemented in 0.18μm CMOS technology. The measured phase noise of the proposed ΔΣ fractional-N frequency synthesizer is -76dBc/Hz in-band and -125dBc/Hz at 1MHz offset from 856 MHz carrier and a loop bandwidth of 50 kHz. The rms jitter is 6.74ps and the integrated phase noise is 2.08^o from 10kHz to 10MHz frequency offset.

Keywords

CMOS digital integrated circuits; delta-sigma modulation; frequency synthesizers; radiofrequency identification; 3rd-order 3-bit single-loop ΔΣ modulator; CMOS technology; UHF RFID reader; bandwidth 50 kHz; digital ΔΣ modulator; feed forward path structure; feedback path structure; fractional-N frequency synthesizer; frequency 1 MHz; frequency 10 kHz to 10 MHz; frequency 856 MHz; loss 125 dB; loss 76 dB; noise shaping; optimized ΔΣ modulator; phase noise; CMOS technology; Feedback; Feeds; Frequency modulation; Frequency synthesizers; Noise shaping; Phase modulation; Phase noise; Poles and zeros; Radiofrequency identification;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave and Millimeter Wave Technology (ICMMT), 2010 International Conference on

Conference_Location

Chengdu

Print_ISBN

978-1-4244-5705-2

Type

conf

DOI

10.1109/ICMMT.2010.5524740

Filename

5524740