Post-CMOS hybrid spin-charge nanofabrics

We propose a hybrid spin-charge fabric with computation in spin domain and communication in charge domain. In nanofabrics based on non-equilibrium physical phenomenon like interference of spin waves, switching times are lower than the thermal relaxation times leading to fast multi-value logic at high fan-in without the exponential performance degradation noticeable in CMOS. While computation is much more efficient than in CMOS, these benefits can be lost due to the communication requirements between spin-wave blocks, when implemented with wave guides. This inspired a new type of hybrid nanofabric with spin wave high fan-in functions connected to an interconnect stack similar to CMOS: our analysis shows a delay reduction of up to 10X (8.64ns) along the critical path for a (511;9) parallel counter implemented in this fabric vs. spin-wave only. Similar benefits are also shown for a CLA adder with ~4.2ns delay reduction for 1024 bit CLA adder.