• DocumentCode
    3227279
  • Title

    Combining unspecified test data bit filling methods and run length based codes to estimate compression, power and area overhead

  • Author

    Mehta, Usha Sandeep ; Dasgupta, Kankar S. ; Devashrayee, Niranjan M.

  • Author_Institution
    Inst. of Technol., Nirma Univ., Ahmedabad, India
  • fYear
    2010
  • fDate
    6-9 Dec. 2010
  • Firstpage
    40
  • Lastpage
    43
  • Abstract
    For SoCs (Sea of Cores!) which contains a large amount of IP cores with pre computed test data, the code based test data compression scheme is more suitable as it does not require any knowledge of internal nodes of IP. The data compression of any partially specified test data depends upon how the unspecified bits are filled with 1s and 0s. In this paper, the five different approaches for don´t care bit filling based on nature of runs are proposed. These methods are used here to predict the maximum compression based on entropy relevant to different run length based data compression code. These methods are also analyzed for test power and area overhead corresponding to run length based codes. The results are shown with various ISCAS circuits.
  • Keywords
    VLSI; data compression; entropy codes; industrial property; integrated circuit testing; runlength codes; IP cores; ISCAS circuits; VLSI test data; area overhead; code based test data compression scheme; compression estimation; don´t care bit filling approach; entropy codes; run length based codes; test data bit filling methods; test power; Decoding; Encoding; Entropy; Filling; System-on-a-chip; Test data compression; Code Based Data Compression Methods; Compression Predicted by Entropy; EFDR; FDR; MFDR; Unspecified Test Data;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on
  • Conference_Location
    Kuala Lumpur
  • Print_ISBN
    978-1-4244-7454-7
  • Type

    conf

  • DOI
    10.1109/APCCAS.2010.5774808
  • Filename
    5774808