An 8T SRAM cell with column-based dynamic supply voltage for bit-interleaving

Lowering power consumption and increasing noise margin have become two central topics in every state of the art SRAM design. Several 8T and 10T cell designs have been reported, improving the cell stability of the conventional 6T. In this paper, we use a fully differential 8T SRAM that removes the half-accessed issue to allow an efficient bit-interleaving implementation. It also consumes less power when compared to the conventional 6T design. A column-based dynamic supply voltage scheme is utilized to improve both the read noise margin and the write-ability. A 128×64-bit of the proposed SRAM has been implemented in a standard 65 nm/ 1V CMOS process. Simulation results reaffirmed that the proposed design has 2x higher noise margin and consumes 46% less power when compared to the conventional 6T design at 1 V supply voltage.