DocumentCode :
3227634
Title :
BusMesh NoC: A novel NoC architecture comprised of bus-based connection and global mesh routers
Author :
Lee, Seungju ; Yanagisawa, Masao ; Ohtsuki, Tatsuo ; Togawa, Nozomu
Author_Institution :
Dept. of Comput. Sci. & Eng., Waseda Univ., Tokyo, Japan
fYear :
2010
fDate :
6-9 Dec. 2010
Firstpage :
712
Lastpage :
715
Abstract :
Network-on-chip (NoC) architectures are emerged as a promising solution to the lack of scalability in multi-processor systems-on-chips (MPSoCs). In this paper, A busmesh network-on-chip (BMNoC) architecture is proposed, together with simulation results. It is comprised of bus-based connection and global mesh routers to enhance the performance of on-chip communication. Furthermore, MPEG-4, H.264 and a hybrid application mixed MPEG-4 and H.264 on our architecture illustrates the better performance than earlier studies and feasibility of BMNoC.
Keywords :
microprocessor chips; network routing; network-on-chip; video coding; BusMesh NoC; H.264; MPEG-4; SoC; bus-based connection; global mesh routers; multiprocessor systems-on-chips; network-on-chip architectures; on-chip communication; Artificial neural networks; Encoding; Lead; Transform coding; A novel NoC architecture; BusMesh NoC (BMNoC); Network-on-Chip (NoC);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-4244-7454-7
Type :
conf
DOI :
10.1109/APCCAS.2010.5774825
Filename :
5774825
Link To Document :
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