System-level analysis of graphene klein tunneling device

We analyze the system-level performance of graphene-based arithmetic logic units (ALUs) enabled by Klein tunneling. Although the proposed graphene device is idealized (many experimental hurdles remain), it is important nonetheless to assess graphene´s system-level prospects for logic applications to provide context for device-level research (the focus of most graphene research to date). We evaluate latency, energy, and area of graphene-enabled ALUs for (i) a 64-bit Brent-Kung adder and (ii) a 64-bit Kogge-Stone adder, both at the 32 nm technology node. The benefit in latency and energy of an ALU realized with graphene-based logic in place of silicon-based logic anticipates a hybrid graphene-silicon microprocessor.