• DocumentCode
    3228088
  • Title

    Data partition analyses for video decoders on PAC Duo platform

  • Author

    Lin, Li-Juo ; Liu, Kuei-Chun ; Chen, Tse-Min ; Wang, Wen-Shan

  • Author_Institution
    Inf. & Commun. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan
  • fYear
    2010
  • fDate
    6-9 Dec. 2010
  • Firstpage
    568
  • Lastpage
    571
  • Abstract
    Two of the most popular video coding standards, MEPG-2 and H.264, are realized on PAC Duo platform, a heterogeneous multi-core SoC containing one ARM core and two PACDSP´s (Parallel Architecture Core DSP). In addition to the optimization of the video software codes, in order to fit to the architecture of PACDSP, the inter-core synchronization required by the dual core implementation must be added to the decoder software. The analysis is also conduced to figure out the roots causing the degradation in performance for the dual core scenarios. The experimental result indicates that the dual PACDSP´s with data partition can gain about 64% and 92.4% of improvement in performance over the single PACDSP for the H.264 constrained baseline decoder and MPEG-2 main profile decoder, respectively.
  • Keywords
    data analysis; digital signal processing chips; synchronisation; system-on-chip; video coding; ARM core; H.264 constrained baseline decoder; MPEG-2 main profile decoder; PAC duo platform; PACDSP; data partition analysis; heterogeneous multicore SoC; intercore synchronization; parallel architecture core DSP; video coding standards; video decoders; video software codes; Decoding; Multicore processing; Multimedia communication; Streaming media; Synchronization; Transform coding; H.264; MPEG-2; PAC Duo; PACDSP; data partition;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on
  • Conference_Location
    Kuala Lumpur
  • Print_ISBN
    978-1-4244-7454-7
  • Type

    conf

  • DOI
    10.1109/APCCAS.2010.5774843
  • Filename
    5774843