A PCI166-compatible 3×VDD-tolerant mixed-voltage I/O buffer

Author

Kuo, Ron-Chi ; Hou, Hsiao-Han ; Wang, Chua-Chin

Author_Institution

Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

fYear

2010

fDate

6-9 Dec. 2010

Firstpage

320

Lastpage

323

Abstract

A PCI166-compatible 3×VDD mixed-voltage I/O buffer with ESD protection consideration is proposed. By using a compact Dynamic gate bias generator to provide appropriate gate drive voltages for the output stage, the I/O buffer can transmit sub-3×VDD voltage level signal without gate-oxide overstress hazard. Besides, the leakage current is eliminated by adopting a Floating N-well circuit. The maximum data rate is simulated to be 166/166/166/100/80 MHz when VDDIO is 5.0/3.3/1.8/1.2/0.9 V, respectively, with an equivalent probe capacitive load of 10 pF.

Keywords

buffer circuits; electrostatic discharge; leakage currents; power supply circuits; ESD protection; PCI166-compatible 3×VDD mixed-voltage I/O buffer; compact dynamic gate bias generator; equivalent probe capacitive load; floating N-well circuit; gate drive voltages; gate-oxide overstress hazard; leakage current; voltage 5 V to 0.9 V; Detectors; Earth Observing System; Electrostatic discharge; Generators; Leakage current; Logic gates; Reliability; I/O buffer; floating N-well circuit; gate-oxide reliability; mixed-voltage-tolerant;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on

Conference_Location

Kuala Lumpur

Print_ISBN

978-1-4244-7454-7

Type

conf

DOI

10.1109/APCCAS.2010.5774846

Filename

5774846