Title :
Feasibility study of VLSI device layer transfer by CMP PETEOS direct bonding
Author :
Tong, Q.-Y. ; Lee, Tae-Hak ; Kim, Woo-Ju ; Tan, T.Y. ; Gosele, U.
Author_Institution :
Max-Planck-Inst. of Microstructure Phys., Halle
fDate :
30 Sep-3 Oct 1996
Abstract :
Reports here the first results of using plasma enhanced CVD TEOS (Si(C2H5O)4) oxide (PETEOS) and associated CMP (Chemical Mechanical Polishing) technology to form a flat layer on the surface of a processed VLSI bulk Si wafer for direct bonding. The undoped PETEOS oxide has also been used as a bonding layer for substrates onto which the IC layer is to be transfered and whose surfaces are not favorable for bonding
Keywords :
VLSI; integrated circuit technology; plasma CVD; polishing; wafer bonding; IC layer; PETEOS direct bonding; VLSI; chemical mechanical polishing; device layer transfer; plasma enhanced CVD TEOS oxide; Annealing; Chemical technology; Glass; Hafnium; Plasma temperature; Semiconductor device measurement; Surface topography; Thermal stresses; Very large scale integration; Wafer bonding;
Conference_Titel :
SOI Conference, 1996. Proceedings., 1996 IEEE International
Conference_Location :
Sanibel Island, FL
Print_ISBN :
0-7803-3315-2
DOI :
10.1109/SOI.1996.552481
