DocumentCode :
3228611
Title :
Computation sharing multiplier using redundant binary arithmetic
Author :
Kattamuri, R. S N Kumar ; Sahoo, S.K.
Author_Institution :
Electr. & Electron. Eng. Dept., Birla Inst. of Technol. & Sci., Pilani, India
fYear :
2010
fDate :
6-9 Dec. 2010
Firstpage :
108
Lastpage :
111
Abstract :
Multiplication is the most time consuming computation for digital signal processing algorithm implementation. In a finite impulse response (FIR) filter, for coefficient multiplication, Computation sharing multiplier was proposed by Kaushik Roy,. He has used natural binary (NB) numbers for implementation of FIR filter. In the present work, redundant binary (RB) number is used in computation sharing multiplication. The implementation of a 16×16 bit multiplier using RB number is found to be faster than that using NB number system with 130nm technology. This speed advantage comes because of the property of RB arithmetic in which no carry propagation occurs while addition of partial products.
Keywords :
FIR filters; adders; redundant number systems; signal processing; coefficient multiplication; computation sharing multiplier; digital signal processing algorithm; finite impulse response filter; natural binary numbers; redundant binary arithmetic; Adders; Delay; Encoding; Finite impulse response filter; Integrated circuit modeling; Multiplexing; Program processors; Computation Sharing Multiplier; Natural Binary Representation; Redundant Binary Representation; Redundant Binary Summation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-4244-7454-7
Type :
conf
DOI :
10.1109/APCCAS.2010.5774869
Filename :
5774869
Link To Document :
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