Achieving high performance to support multicast traffic in a parallel packet switch with space division multiplexing expansion

A parallel packet switch (PPS) is a switch in which the memories run slower than the line rate. Till now, most of theoretical researches on PPS simply rely on increasing the speedup of switch-layers to emulate a "First-come First-serve" output queued (FCFS-OQ) switch. However, when the input traffic is multicast pattern, the speedup requirement of a N-port PPS will increase to 2radicN + 1. Clearly, the resulting explosive increase of speedup makes these traditional PPS schemes impractical for any meaningful N. In this paper, we propose to use a completely new and practical multicast architecture for PPS to efficiently support multicast traffic rather than simply increasing speedup as multicast schemes of PPS before. We call the resulting multicast PPS as a PPS with space division multiplexing expansion (SDME PPS). Then, we prove that when loaded with multicast traffic, a bufferless SDME PPS with speedup 2 can emulate a FCFS-OQ switch within a small relative queuing delay bound. Furthermore, we show that a highly practical SDME PPS can be designed by allowing small fixed-size coordination buffers in both demultiplexers and multiplexers. We determine the size of small buffers and show that the resulting buffered SDME PPS can emulate a FCFS-OQ switch within a slightly larger delay bound