Implementation of low power FFT structure using a method based on conditionally coded blocks

This paper proposes a coding technique which reduces switching activity hence power consumption in FFT structures. This technique involves a sequential creation of conditionally coded blocks in the inputs of FFT structure. These blocks are then converted to low switching activity blocks using the proposed technique and are concatenated to each other in a sequential order to produce the optimized output. To increase the efficiency, the scheme is applied recursively after each concatenation. The performance of proposed method has been tested and it was found that with respect to 2´s complement, the average switching activity is reduced by 38% for different bus lengths. The significant reduction in switching activity leads to power savings of 35% for a 16-bit bus. The hardware, used for encoding and decoding purposes, has been designed using Magma© tools.