Notice of RetractionAnalysis of parasitic bottom capacitance in n- and p-type Si-nanowire field effect transistors on bulk

Notice of Retraction

After careful and considered review of the content of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE´s Publication Principles.

We hereby retract the content of this paper. Reasonable effort should be made to remove all past references to this paper.

The presenting author of this paper has the option to appeal this decision by contacting TPII@ieee.org.

In this paper, we analyzed the parasitic bottom capacitance of n- and p-type Gate-All-Around nanowire FET fabricated on the Bulk-Silicon. We fabricated 100 × 100 nanowire array and measured the inversion capactance C_gsd which is Gate to Source/Drain capacitance while floating the Body contact. In spite of floating Body condition, the parastic bottom capacitance turned on through embedded-SiGe layer by which nanowire is compressively stressed and C_gsd is distorted. In this paper the mechanism of generating the parasitic bottom capacitance is analyzed, using the energy band diagram. Also the influence of device structure including SiGe layer has been simulated.